eCircuit  Center

### RC Low-Pass Filter

CIRCUIT

Here’s a simple circuit for you to dive into running SPICE simulations and plotting results.

What is the purpose of this circuit? Basically it has two roles: to pass the desired low frequency signals and stop the unwanted high frequency signals.

TIME RESPONSE

Open the netlist file “lpfilter1.cir” with your SPICE simulator. Most simulators display the netlist in a text editor window. You can view, modify and save the netlist from this window.

Run a simulation. (TopSpice users click the traffic light on the toolbar; PSPICE users click the blue square.) View the transient (time) analysis at the input V(1) and output V(2). For R1=1k, C1=0.032uF and sinewave generator at 2kHz, you should see the 2 kHz sinewave (desired signal) pass through to the output V(2) except for a slight decrease in signal and slight shift in time.

Now change the sinewave frequency to 40 kHz by editing the voltage source line to look like

VS       1          0          AC      1          SIN(0  1 40KHZ)

Save the file and run another simulation. Assume this 40 kHz signal represents the undesirable noise in a system. Did the filter reduce the 40 kHz signal?

CUTOFF FREQUENCY

As stated above, the circuit has two roles: to pass the desired low frequency signals and stop the unwanted high frequency signals. But at what frequency does the filter change its behavior from passing the low ones to stopping the high ones. This is called the cut-off frequency.

For R1=1k and C1=0.032uF you get fc = 5kHz. Run a simulation. Plot the AC (frequency) sweep results for the output magnitude VM(2) and phase VP(2). What does the magnitude look like before and after 5kHz?

SPICE FILE

Download the file or copy this netlist into a text file with the *.cir extention.

```LPFILTER1.CIR - SIMPLE RC LOW-PASS FILTER
*
VS	1	0	AC	1	SIN(0	1	2KHZ)
*
R1	1	2	1K
C1	2	0	0.032UF
*
* ANALYSIS
.AC 	DEC 	5 10 10MEG
.TRAN 	5US  500US
* VIEW RESULTS
.PRINT	AC 	VM(2) VP(2)
.PLOT	AC	VM(2) VP(2)
.PRINT	TRAN 	V(1) V(2)
.PLOT	TRAN 	V(1) V(2)
.PROBE
.END```

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