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Adding 2nd and 3rd Poles

R1 = 1e6  Choose R1  
K1 = Aol /
R1 = 0.01 
Calc gain of the G1 in A/V to achieve Aol.  
C1 = 1 / (2 * pi *
fp1 * R1) = 1.59e9 
Calc C needed to achieve pole fp=100Hz 
2nd and 3rd poles – These stages are unity gain stages. The DC gain is
determined by the current from G2 and G3 flowing into R2 and R3, respectively:
V(20) = I2*R2 = 1 and V(21) = I2*R2 = 1. To get poles
fp2 = fp3 = 4.8 MHz, simply calculate:
R2 = R3 = 1e6  Choose R2, R3  
KG2 = 1 / R2 = 1e6 KG3 = 1 / R3 = 1e6 
Calc gain of the G2 and G3 in A/V to achieve unity gain.  
C2 = 1 / (2 * pi *
fp2 * R2) = 3.314 C3 = 1 / (2 * pi * fp3 * R3) = 3.314 
Calc C needed to achieve poles. 
REALITY CHECK! One discovery you’re bound to make  simulation is NOT an exact science. Creating models involves some science, engineering, tweaking, art and finally knowing when to say “it’s close enough”. Don't sweat it. Even the actual devices won’t work exactly as specified. Their datasheet represents typical behavior, not the full swing of variations that roll off the production line.
ONE MORE POLE!
WARNING! There's another pole that's buried in the data sheet (and the SPICE model)! The closedloop test is usually performed with a specific load capacitance, such as CL = 100 pF. So where's the pole? It's formed by the output resistance of the op amp model ROUT and the load capacitance CL. This pole adds even more negative phase pushing the behavior towards more overshoot and ringing.
ROAD TEST
OPENLOOP TEST (AC ANALYSIS)
Let's use the noninverting amplifier to test drive our op amp SPICE model.
Initially, we test it openloop by setting R1 = 1 ohm (short) and R2=1e12 (open). For the load, set RL=10k and CL=1pF (effectively no capacitance). To run an AC Analysis, remove the "*" in front of the .AC command and plan an "*" in front of the .TRAN command..
CIRCUIT INSIGHT The op amp is driven by AC source VS. There are essentially no feedback resistors here – its running openloop. Try out the model by running a simulation and plotting the AC magnitude VM(3). Can you see the DC gain = 100k V/V and the firstpole at fp1 = 100 Hz? What is the unity gain frequency? Try changing the YAxis to a log scale to get a better view at high frequencies. If your plotting in dB, the unitygain level is 0 dB.
Now open a new plot window and display the phase VP(3). Does the first pole add 90 deg above the first pole? Check out the phase near 4.8 MHz  do the 2nd and 3rd poles kick in adding another 45 deg for a total of about 135 deg? If so, your ready to close the loop on your device and hit it with a step input in the time domain.
CLOSEDLOOP TEST (TRANSIENT RESPONSE)
Let's close the loop on out amplifier and set it unity gain by setting R1 = 1e12 (open) and R2=1 (short). For the load, set RL=10k and CL=100pF. To run an Transient Analysis, remove the "*" in front of the .TRAN command and plan an "*" in front of the .AC command.
According to the data sheet, the transient response should have a rise time (10% to 90%) of 0.2 us and an overshoot of 10% max.
CIRCUIT INSIGHT The op amp is driven by step input of 1 V. Run a simulation and plot the Transient Response at V(3). What is the rise time and overshoot? It looks like the 10% to 90% rise time is about 0.2 us. Very nice! More good news: you've got some overshoot and ringing  something not easily achievable without the 2nd and 3rd poles. However, the overshoot looks a bit low at only 3%, not quite the 10% shown.
HANDSON DESIGN Okay, let's do some tweaking. There are two things I usually do. First, lower the 2nd and 3rd pole by 10% or 20%, and second increase ROUT from 100 ohms to 125 or 150 ohms. Try a few tweaks and rerun the simulation. As you lower the poles and raise ROUT, the overshoot should grow. Are you able to raise the overshoot to near 10%? Note that the 10% is a max number and no typical is specified. So it's okay if you don't quite reach 10%.
Your actual circuit will likely behave a bit different due to device variations and some stray capacitance on the PCB. But the simulation has opened your eyes to real world op amp behavior including potential overshoot and ringing.
SIMULATION NOTES
For a description of all op amp models, see
Op Amp Models.
This op amp model can be used for many of the op amp
circuits available from the Circuit
Collection page.
SPICE FILES
Download the file or copy this netlist into a text file with the *.cir extension.
OP_2ND_3RD_POLES.CIR * * SIGNAL SOURCE VS 1 0 AC 1 PWL(0US 0V 0.01US 1V 10US 1V) * NON INVERTING AMP R1 0 2 1 R2 2 3 1e12 XOP1 1 2 3 OP_TL062 * RL 3 0 10k CL 3 0 1pF * OP AMP MODEL * * Device Pins In+ In Vout .SUBCKT op_tl062 1 2 82 * * INPUT R RIN 1 2 1e9 * * AMPLIFIER STAGE: GAIN, POLE, SLEW * Aol=10000, fu=1000000 Hz G1 0 10 VALUE = { 1e2 * V(1,2) } R1 10 0 1e6 C1 10 0 1.59159e9 * * 2ND POLE G2 0 20 10 0 1e6 R2 20 0 1e6 C2 20 0 3.3e14 * * 3RD POLE G3 0 30 20 0 1e6 R3 30 0 1e6 C3 30 0 3.3e14 * * OUTPUT STAGE EBUFFER 80 0 30 0 1 ROUT 80 82 100 .ENDS * * ANALYSIS ************************************* *.TRAN 0.05US 2US .AC DEC 20 1 100MEG .PROBE .END
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